Integrated circuits typically use multiple field effect transistors fabricated using a wafer of semiconductor material. The need to integrate more functionality into an integrated circuit has prompted the semiconductor industry to seek approaches to shrink, or scale, the size of individual field effect transistors and other devices commonly integrated into the integrated circuit. However, scaling devices to smaller dimensions may cause a multitude of undesirable consequences.
Generally, field effect transistors are planar device structures that operate by electronically varying the conductance of the semiconductor material in a channel region along which carriers flow between a source region and drain regions also defined in the semiconductor material and separated by the channel region. In n-channel field effect transistors of complementary metal-oxide-semiconductor device pairs or structures, electrons are responsible for conduction in the channel, and in p-channel field effect transistors of complementary metal-oxide-semiconductor device structures, holes are responsible for conduction in the channel. Output current is controlled by voltage applied to a gate conductor, which is located above the channel region at a location between the source region and drain region. The gate electrode is insulated from the channel region by a thin intervening gate dielectric, which may be silicon dioxide, and is normally flanked by spacers of a dielectric material that is typically silicon nitride.
One approach for improving the performance of scaled field effect transistors is to strain the crystal lattice in the channel of the transistors with a stressed insulating layer or liner overlying the source/drain regions and gate conductors. A conformal layer of silicon nitride is frequently used as the stress liner. Deposition conditions for the stress liner are selected such that tensile strain is induced in the channel region of n-channel field effect transistors and compressive strain is induced in the channel region of p-channel field effect transistors, in the direction of channel current. Efficient transfer of stress to the channel regions depends upon the stress liner being in close proximity to the peripheral edges of the gate conductors. Unfortunately, silicon nitride and other common stress liner materials have a relatively high dielectric constant that accentuates the parasitic capacitance between the gate electrode and the source/drain regions. Consequently, adding the stress liner conflicts with another goal for maximizing device performance in scaled field effect transistors, namely reducing the parasitic capacitance between the gate electrode and the adjacent source/drain regions. Parasitic capacitance gives rise to a delay in the operation of the field effect transistor and hence, limits the operation speed that can be achieved by the device.
The spacers flanking the gate conductor may be removed to improve the transfer of stress from the liner to the channel regions. However, the sidewalls of the gate conductor and the source/drain diffusions are still separated by the dielectric materials of the liner Other dielectrics having lower permittivity than nitride, such as silicon oxide, may be used for the spacer material to reduce parasitic capacitance. However, to promote effective stress transfer the spacer must be made thin, which is undesirable for low parasitic capacitance. Thus, reducing the parasitic capacitance between the gate electrode and the adjacent source/drain regions and inducing strain in the channel region are competing objectives in the scaling of field effect transistors.
What is needed, therefore, are semiconductor device structures for field effect transistors and methods for fabricating field effect transistors that overcome these and other disadvantages of conventional semiconductor device structures and fabrication methods.